1. Field of the Invention
The present invention relates to clock converters. More particularly, the present invention relates to a circuit configured to convert a clock signal having a complimentary metal oxide semiconductor (CMOS) duty cycle level to a clock signal having a current mode logic (CML) duty cycle level.
2. Background Art
High speed communication systems utilize a variety of different approaches to optimizing the performance of their associated system clocks. As clock rates increase to accommodate the demands of these high speed communications systems, the room for clock tolerances decreases. For example, small variations in a clock""s output signal, known as jitter, may have a crippling effect on the operation and synchronization of interrelated clock dependent circuits. Furthermore, clock stability may be critical to the operation of logic circuits that are dependent upon the rising and falling edges of the clock""s output signal. Thus, even a small amount of jitter in a clock""s output signal may significantly alter the clock signal""s duty cycle, consequently degrading the communication system""s overall performance.
Particular integrated circuit technology types, such as CMOS and CML, are typically associated with specific duty cycle values. For example, CMOS systems normally produce signals having a duty cycle around 25% and CML systems normally produce signals having a duty cycle around 50%. The higher duty cycle characteristics of CML make it better suited for higher speed applications. Also, as known in the art, CMOS circuits operate at logical high voltage levels from about 0 to 2.5 volts, thus creating about a 2.5 volt peak-to-peak swing. On the other hand, CML level circuits operate around 1.5 volts to 2.5 volts, thus producing a 1 volt peak-to-peak swing. Some applications, however, may require attributes of both CMOS and CML technology. One approach to satisfying this requirement is the ability to convert CMOS signals into CML signals.
For example, a variety of conventional CMOS based frequency divider circuits receive a master clock signal as an input and produce a number of multi-phase signals as an output. These multi-phase divider circuits may be used to reduce the overall number of oscillators required on a given semiconductor chip, for example, thereby making available additional room on the chip to place more circuitry. Although beneficial in this capacity, these CMOS multi-phase divider circuits are inherently slow and their low duty cycle signals are susceptible to supply coupling, which causes jitter. As a result, there is a need for a device to convert a CMOS multi-phase output clock signal having a duty cycle of about 25% into a CML level clock signal having a duty cycle of at least 50%.
Consistent with the principles of the present invention as embodied and broadly described herein, an exemplary circuit includes a first pair of transistors having gates thereof respectively forming first and second circuit inputs, sources thereof being connected together, and drains thereof being connected together and forming at least a first circuit output. The exemplary embodiment also includes a second pair of transistors having gates thereof respectively forming third and fourth circuit inputs, sources thereof being connected together, and drains thereof being connected together and forming at least a second circuit output. Sources of the first pair of transistors are connected to the sources of the second pair of transistors.
Features and advantages of the present invention include the ability to convert a lower duty cycle clock signal in CMOS to a higher duty cycle clock signal in CML. Such a circuit may be ideal for use where both CMOS and CML technologies are used together, such as the low jitter and high speed environments of variable control oscillators used in phase locked loop (PLL) circuits. Additional features include the ability to insure excellent rejection of common mode voltages associated with circuit power supplies.